High-speed integrated circuit memory devices may include a dynamic random access memory (DRAM), an input/output unit that receives an external signal, and an interface logic unit that receives a command from the input/output unit and decodes the received command. The DRAM may be tested in a direct access test mode. In the direct access test mode, test signals output by low frequency testing equipment bypass the interface logic and proceed directly to the DRAM, so that the low frequency testing equipment can test the DRAM.
FIG. 1 is a block diagram of a high-speed integrated circuit memory device including an input/output circuit. Referring to FIG. 1, a conventional high-speed memory device 101 includes first through eighth pads P0 through P7, first through eighth input pipelines 121 through 128, first through fourth buffers 131 through 134 and a memory cell array such as a DRAM cell array 111. The high-speed memory device 101 receives a test row address strobe signal (TRASB), a test column address strobe signal (TCASB), a test write enable signal (TWE), a test latch enable signal (TWL), a test clock signal (TCLK), a row address signal (RADR) and a column address signal (CADR) from external of the device 101.
FIG. 2 shows the waveforms of signals for writing data in the DRAM cell array 111 of FIG. 1. A method of writing data in the DRAM cell array 111 of a high-speed memory device in the direct access test mode will now be described referring to FIGS. 1 and 2.
In order to select memory cells of the DRAM cell array 111, the test write enable signal TWE is activated to logic high. In this state, when the row address signal RADR and the column address signal CADR are input to the DRAM cell array 111, particular cells of the DRAM cell array 111 are selected. The row address signal RADR is input to the first through fourth buffers 131 through 134 via the first through fourth pads P0 through P3 when the test row address strobe signal TRASB is activated to logic low. The column address signal CADR is input to the first through fourth buffers 131 through 134 via the first through fourth pads P0 through P3 when a column latency signal COLLAT which is generated when the test column address strobe signal TCASB is activated to logic low, is activated to logic high. The direct access test signal PDA is activated to logic high in the direct access test mode, so that the row and column address signals RADR and CADR input to the first through fourth buffers 131 through 134 are transmitted to the DRAM cell array 111 to select the particular cells of the DRAM cell array 111.
After the row and column address signals RADR and CADR are input to the DRAM cell array 111, the test clock signal TCLK is generated. During four cycles of the test clock signal TCLK, data to be written in the DRAM cell array 111 from external of the memory device is latched to the first through eighth input pipelines 121 through 128 via the first through eighth pads P0 through P7. The data latched to the first through eighth input pipelines 121 through 128 is written to the DRAM cell array 111 when a column cycle signal COLCYC that is generated as the test column address strobe signal TCASB is inactivated to logic high, is activated to logic high.
As described above, a test pad is allocated for each data bit to test the DRAM cell array 111 of a conventional high-speed memory device 101. Accordingly, it may be difficult for the test equipment to test several high-speed memory devices simultaneously due to the limited number of test pads. Thus, long times may be needed to test several high-speed memory devices. Also, a conventional DRAM memory device may not receive data via the first through eighth input pipelines 121 through 128 during four cycles of the test clock signal TCLK. Therefore, the time for testing the DRAM memory cell array of a high-speed memory device may increase significantly compared to testing a conventional memory device.